There is an on-going trend towards smaller on-chip interconnect wiring dimensions, especially in terms of the width of the interconnect structures which are evolving towards less than 50 nm. Consequently, a constant need for improved copper plating techniques exists. Interconnect structures are typically formed by filling trenches or holes in a dielectric layer, wherein these trenches or holes are first lined with a barrier layer, and possibly a seed layer. The barrier layer prevents migration of Cu into the surrounding dielectric, whereas the seed layer is often necessary as a consequence of poor nucleation of Cu onto the barrier layer.
For the barrier layer, Tantalum has been used. The seed layer is often a physically or chemically deposited Cu layer. The insufficient thermal and electrical conductivity of Ta however, and the search for barrier layers that do not require a separate seed layer, but which allow directly depositing a Cu layer (in other words combined barrier/seed layers), has led to alternatives for Tantalum.
In ‘Electrodeposition of Cu on Ru barrier layers for damascene processing’, Moffat et al., Journal of Electrochemical Society, 153(1) C37-050 (2006), a method for directly electroplating Cu onto a Ruthenium barrier layer is described. The removal of oxides from the Ru-layer is described as a necessary pre-treatment step, possibly by treating the Ru-layer with a deaerated sulphuric acid solution.
Cu plating on the barrier/seed layers occurs through nucleation and growth of Cu islands on top of the Ru or RuTa barrier/seed layer, which coalesce into a continuous Cu film. Achieving a high copper island density is extremely important in Cu plating of narrow lines (<50 nm or <32 nm) and other small features, where extremely high island density (>1011 cm−2) is needed to achieve defect-free fill. In order to plate Cu films less than 15 nm thick, and fill the narrow lines, one has to have a good control over Cu island density, i.e. extremely high Cu island densities are needed. The island density may be influenced by adjusting parameters such as current (potential), bath composition, concentration of additives, etc., but also by modifying the substrate properties. For example, as stated with reference to the article by Moffat et al., removing a thin oxide film from a Ruthenium surface has a strong effect on Cu plating, and increases Cu island density. However, in the case of RuTa surfaces, the commonly used approach of forming-gas-anneal (FGA=anneal with H2/N2: e.g. 10% H2 in N2) does not improve RuTa substrate properties enough. Also, electrolytic “cleaning” with H2SO4 does not improve the RuTa surface enough, since H2SO4 has no effect on Ta.
Thus, plating high Cu island density on Ru-comprising surfaces of substrates, in particular RuTa surfaces, with good adhesion between Cu film and RuTa layers is still challenging, and further improvements in the pre-treatment methods and other aspects of metallization technology are needed.